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digital smps controller preliminary data i w2202 revision 1.1 page 1 1 application blue - angel - compliant pfc - controlled switch - mode power supplies up to 150 watts. 2 features pulsetrain ? regulation allows voltage, current and pfc to be controlled independently primary - only feedback eliminates optoisolators and simplifies design no loop compensation components required 1% regulation over a 100:1 load variation built - in soft - start adaptive pulsetrain regulation keeps the bulk capacitor voltage below 400v operates in critical discontinuous conduction mode (cdcm) low start - up and su pply current reduced emi noise so - 8 package 3 benefits ideal for single - stage, single - switch power factor correction (pfc) enables 97% power factor correction resulting in en6100 - 3 - 2 compliance smartskip mode provides low standby dissipation of the power sup ply enabling blue angel compliance efficiency greater than 85% across line and load variation universal input (85 - 270v, 50 - 60 hz) low parts count reduced design time due to the elimination of loop compensation design 4 description the IW2202 is a digital switching mode power supply controller for pfc applications. its is typically used with the pfc - corrected bifred (boost integrated with flyback rectifier/energy storage dc/dc ) topology, shown in figure 1 . the bifred topology is a single - stage, single - switch topology that combines a boost converter with an isolated flyback converter, achieving power - factor correction with a low parts count. an IW2202 - based power supply looks like a resistor to the ac line. unlike attempts to control the bifred topology with analog controllers, the all - digital IW2202 provides a near - unity power factor without placing high voltage stresses on the bulk capacitor. the IW2202 uses a proprietary new digital control technology called pulsetrain ? to achieve efficiencies in excess of 85% across a wide load range, and across the universal input range of 85 - 270vac, 50 - 60 hz. internally, the i w2202 uses real - time waveform analysis to determine crucial circuit parameters. the reflected secondary voltage of the flyback transformer is sensed at precisely calculated times to determine the secondary voltage, the transformer reset time, and the idea l zero - voltage switching point measurements are performed during the off time of every cycle, and the results determine what is done on the next cycle. the dynamic response time of the circuit is less than half a cycle. ac input gnd vout boost (bulk) capacitor switch boost inductor auxiliary winding output 85-270 v, 50-60 hz IW2202 current sense flyback winding + figure 1 . IW2202 system concept www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 2 5 pin description v sense v aux v in 1 2 3 4 8 7 6 5 gnd i sense output pgnd v cc IW2202 pin # name type pin description 1 v cc power input power supply for control logic and voltage sense for power - on reset circuitry 2 v sense analog input secondary voltage sense (when used with optional secondary opto - isolator feedback). tied to v aux in normal configuration 3 v in analog input line voltage sense. used to monitor rectified line voltage for pfc control 4 v aux analog i nput feedback voltage from auxilary winding. used to monitor output voltage waveform 5 i sense analog input primary current sense. used for cycle - by - cycle peak - current control 6 gnd signal ground analog/digital ground 7 pgnd power ground power ground 8 output digital output gate driver for external mosfet switch. 6 absolute maximum ratings parameter min max units supply voltage 0 15 v input voltage on v sense , v in , v aux, i sense - 0.3 6.3 v power dissipation at t a 25 c 800 mw storage temperature (t st g ) - 65 150 c lead temperature, while soldering for 10 seconds 300 c www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 3 7 electrical characteristics unless otherwise specified, these specifications apply for v cc = 12v, t a 70 c. (see note 1 .) symbol parameter test conditi ons min typ max units feedback / auxiliary / pfc section (pins 2, 3, and 4) v ir input voltage range 0 5 v i ir input current range 0.1 1 m a v ref internal voltage reference (note 2 ) 1.182 1.2 1.218 v isense section (pin 5) i sense buffer gain 4.75 5 5.25 v/v input voltage 0 5 v input current 0.1 2 m a v sd output shutdown voltage (note 3 ) 1.5 5 v output section (pin 8) v ol output low level i sink = 2 00ma 0.5 1 v i sink = 20ma 0.2 0.4 v v oh output high level i source = 200ma 10 11 v i source = 20ma 10 11 v t r rise time (note 4 ) t a = 25 c, c l = 1500pf 30 50 ns t f fall time (note 4 ) t a = 25 c, c l = 1500pf 30 50 ns t on_max maximum switch on time (note 5 ) 5.1 6 6.9 m s start - up section (pin 1) v su start - up threshold (note 1 ) 13.5 14 14.5 v min operating voltage after turn - on 9.5 10 10.5 v supply voltage section (pin 1) i su start - up current v cc = 13v 0.5 1 ma i cc supply current (operating) 10 v cc 13.2 12 ma v uvp under - voltage protection 7 7.8 8.6 v v ov p over - voltage protection v su +1.0 v notes: 1. vcc must be brought aboe the start - up threshold before setting to its operating value (nominally 12v). 2. v ref is the internal voltage reference. it is not brought out to a pin. 3. when the voltage on the isense pin e xceeds v sd , all gate pulses are suppressed. 4. not tested, but guaranteed by design. 5. the switch will be turned off after this amount of on time if i peak has not been reached, placing a lower limit on switching frequency. www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 4 8 application example ac input gnd d 6 l 1 r 6 q 1 c 4 pgnd t 1 vout c 2 d 5 r 5 br1 d 3 d 4 c 3 r 7 r 8 snubber bulk capacitor switch current sense r 2 d 1 r 1 start- up c 1 auxiliary winding chip power auxiliary voltage line voltage sense boost inductor flyback windings blocking diode output rectifier, filter capacitor iwatt 2202 digital smps controller 100-250 v, 50-60 hz output 8 2 vsense 1 vcc isense 5 gnd 6 pgnd 7 4 vaux 3 vin IW2202 vcc from chip power r 4 d 2 r 3 item description q1 mosfet switch. l1, c1, d6 boost converter section of the bifred boost/flyback system. the capacitor c1 provides the energy for the flyback transformer. see sections 11.4 and 12.7 . t1 the flyback winding provides power to the load. the reflected voltage on the auxiliary winding is used by the real - time waveform analysis circuit. the auxiliary winding also provides power for the IW2202 . d1, c4, startup chip power supply. r1, r2 voltage divider to scale the auxiliary voltage to the appropriate value. clamping diode d2 minimizes negative voltage on the vaux pin. see section 12.6 . r7, r8 voltage divider for the li ne voltage sense circuit. fixed values: r7= 500k, r8=1k. r4, r5, r6 current sense circuit. resistor values set the peak current. see section 12.3.1 . figure 2 . IW2202 - based p ower supply with single - stage, single - switch active pfc www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 5 9 block diagram power- on reset output v cc pgnd control logic driver gnd v sense v aux v in voltage reg. i sense primary current sense reflected voltage waveform detect waveform analyzer (opt.) secondary voltage sense pfc line voltage sense cycle timing rising edge (zvs) falling edge (constant ipeak) cycle selection power sense skip figure 3 . conceptual block diagram of the IW2202 v aux threshold t n+1 t n+2 t n t n+3 v aux low high high low the voltage on the auxiliary winding, v aux , is measured at a point near the end of the off period. this voltage is compared to the v aux threshold. if it is higher, the next cycle is a sense cycle. otherwise, the next cycle is a power cycle. switch state pulsetrain state cycle n+1 cycle n+2 cycle n+3 cycle n on power cycle sense cycle sense cycle power cycle on off off on on off off figure 4 . power pulses, sense pulses, and the reflected secondary voltage on the auxiliary winding www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 6 10 pulsetrain regulation rather than using pulse - width or pulse frequency modulation to achieve output voltage regulation, pulsetrain controls output volt age through the presence or absence of power pulses. if the output voltage is below the desired level, power pulses are emitted continuously until the desired level is reached. if the output voltage is higher than the desired level, sense pulses are sent i nstead of power pulses. a sense pulse has a much shorter on time than a power pulse, and transfers much less energy. see figure 4 . a sense cycle has the same period as the preceding power cycle, but the on time is set to one - fourt h that of the power cycle. since primary current ramps linearly with on time, the peak current of a sense pulse is also only one - fourth that of a power pulse. thus, a sense cycle only transfers one - sixteenth as much energy as a power cycle. under most load conditions, regulation is achieved through a mix of power cycles and sense cycles. under extremely low - load conditions, no power pulses are sent. instead, sense cycles alternate with skip cycles. it is important to recognize that pulsetrain does not depen d on the precise width of the pulses to maintain regulation. if the output voltage is lower than the desired level, the next cycle will contain a power pulse. if the output voltage is above the desired limit, the next cycle will contain a sense pulse. the pulsetrain controller will optimize the ratio of power pulses to sense pulses to keep the output voltage constant. the frequency and duty cycle of the pulses can change, but this does not affect voltage regulation. this situation is very different from the situation with analog technologies, such as pwm/pfm - based controllers, which are forced to attempt to meet all their goals through the adjustment of pulse geometry, which forces unwanted trade - offs. as will be shown in the next section, pulsetrain modulat ion takes full advantage of its ability to pursue multiple simultaneous goals, combining the flexibility of pulsetrain regulation with the precision of real - time waveform analysis, resulting in ultra - fast dynamic response and simplified circuit design. 11 rea l - time waveform analysis figure 5 shows the effect of a sense pulse on the transformer?s primary winding, measured at vdrain. as you can see, this waveform contains quite a bit of ringing. this ringing is highly organized, consis tent from cycle to cycle, and its onset pinpoints important events in the cycle. in a flyback system, the reflected voltage seen during the switch?s off time reveals the secondary voltage, plus additional circuit information, including leakage inductance, transformer reset time, resonant frequency, and secondary diode characteristics. all this information is easily read on an auxiliary winding. this information renders secondary feedback unnecessary. the choice between reading the reflected voltage on the p rimary winding or on an auxiliary winding is somewhat arbitrary. if taken from the primary, the voltage centers around vin (the instantaneous line voltage). if taken from an auxiliary winding, the voltage centers around zero. the auxiliary winding can also provide power for the device. real - time waveform analysis uses the information in the reflected voltage to extract secondary voltage and transformer reset time. these voltage measurements are made on every cycle , and each cycle?s measurement determines t he next cycle?s pulse type. traditional voltage regulators use space - average sensing, averaging the voltage over multiple cycles. this causes the loss of a great deal of information and introduces delays, slowing the response of the controller and raising the issue of loop instability. real - time waveform analysis, on the other hand, does not perform averaging, but determines the next cycle?s switching decisions from the current cycle alone. the time delay between measurement and correction (dynamic response ) is thus extremely short, being less than the off time of a single cycle. the system is inherently stable. there is no need for loop compensation. www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 7 v drain t cds this value of i d2 will always be the same, given a constant d t. ringing due to leakage inductance. the off time of a sense pulse must be wider than the decay time of this waveform. this ringing is due to the resonance of the magnetizing inductance and switch capacitance, and indicates a fully reset transformer. resonance is easily detected when voltage excursions cross v in . two successive crossings give t res /2. very consistent from cycle to cycle. v in 0 if the transistor is switched back on at this point, we will come very close to true zero-voltage switching. in addition, we will achieve critically discontinuous conduction mode; that is, we will eliminate dead time between cycles while guaranteeing that we remain in discontinuous mode. the slope of this reflected voltage represents the voltage-current characteristics of the secondary side . if the voltage is read at a consistent time before the transformer is fully discharged, this d v is a constant, and we achieve a very accurate reading of the secondary output voltage. v drain = v in +(v out + d v)*n pri /n sec on off switch state d t secondary diode current t cds is the off-time that will achieve critically discontinuous conduction mode and zero- voltage switching. in iwatt products, this time is measured with every sense pulse. voltage is measured here t res /2 d t t res /4 figure 5 . information available to waveform analysis www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 8 11.1 zero - voltage switching pulsetrain achieves zero - voltage switching (zvs) by using the resonance (ringing) that occurs in discontinuous - mode flyback circuits. this resonance occurs after the secondary current falls to zero, indicating the transition fro m power transfer to open - circuit conditions. t 1 t 2 t zvs = (t 2 -t 1 )/2 t zvs is measured on sense cycles vaux=0 zvs algorithm (power cycles): 1. wait for vaux < 0 2. wait an additional t zvs 3. turn on switch post-conduction resonance vaux = -vin*npri/naux vaux = vout*nsec/naux figure 6 . auxiliary voltage and zero - voltage switching as shown in figure 5 , post - conduction resonance is a damped oscillation t hat falls very close to zero volts on its first cycle. zero - voltage switching can be achieved very easily, simply by measuring the resonant period on a sense cycle, and switching the output transistor when the voltage is closest to zero on subsequent power cycles. the algorithm for zvs is shown in figure 6 . on each power cycle, pulsetrain waits for the primary voltage to drop below v in , (on the auxiliary winding, this occurs when the voltage goes negative). this indicates that we a re in the post - conduction resonance. after this event, the controller waits an additional d t that will take us to the minimum voltage, then turns on the switch for the next power or sense cycle. the time between the zero - crossing on the auxiliary winding a nd the minimum primary voltage is estimated as being one - half the time between the negative - going zero crossing and the positive - going zero - crossing, as shown in figure 6 . given the geometry of the resonant signal, this estimate i s extremely accurate. by achieving zero - voltage switching, we also achieve critically discontinuous conduction mode, because we have turned the transistor back on immediately after the transformer?s magnetic field has reset. this eliminates dead time betw een cycles, fully utilizing the output transformer. as a result, the transformer operates at lower flux levels than traditional technologies, resulting in lower core losses and thus higher efficiencies. because the waveform is being monitored in real time, critically discontinuous conduction mode is maintained across all variations in line and load conditions. in addition, this method of extracting maximum performance from the inductor is insensitive to component variations, since the circuit behavior is me asured, not assumed. 11.2 primary - only feedback pulsetrain uses primary - only feedback, measuring the secondary voltage by analyzing its reflected voltage as seen by an auxiliary winding. this reflection reveals what is happening at the transformer secondary. ho wever, the voltage at the load differs from the secondary voltage by a diode drop and ir losses. the diode drop is a function of current, as are ir losses. thus, if the secondary voltage is always read at a constant secondary current, the difference betwee n the output voltage and the secondary voltage will be a fixed d v. furthermore, if the voltage can be read when the secondary current is small, the d v will also be small. as shown in figure 5 , secondary current has a linear ramp down to zero. zero secondary current is signaled (on the reflected voltage waveform) by the beginning of post - conduction resonance. using resonance as a marker, is a simple matter to calculate a fixed d t that will pinpoint a time where secondary diode curr ent is still flowing, but is very small. the exact value of d t is not crucial, so long as it places the measurement at a point where current is still nonzero. d t is recalculated on sense cycles. measuring voltage on sense cycles uses the same d t as on pow er cycles. because the slope of the secondary current ramp is independent of on time, the current at a fixed d t is the same, regardless of whether the cycle is a sense cycle or a power cycle. 11.3 constant peak current like the decision to turn the transistor o n, the decision to turn the transistor off is controlled by real - time waveform analysis -- this time in the current domain. the maximum desirable primary current, ipeak, is set with external resistors. on every power cycle, the power transistor is kept on until the primary current ramps up to ipeak. when this level is reached, the transistor is turned www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 9 off. thus, the point at which the transistor is turned off is controlled by the current waveform, while the point at which it is turned on is controlled by t he voltage waveform. if the line voltage is very high, the current will ramp up quickly, and the on time of the switch will be short. if the line voltage is very low, the current will ramp slowly, and the on time will be long. low line voltage results in longer on times before peak current is reached, resulting in long cycle times (and relatively low switching frequencies). critically discontinuous mode is maintained. high line voltage results in shorter on times, because peak current is reached more quickly. short on times lead to short cycle times (high switching frequency). critically discontinuous mode is maintained. vdrain iswitch isec vdrain iswitch isec on off on off on off on off on off on off figure 7 . constant peak current switching because of this, the output frequency of the pulsetrain regulator varies to accommodate changing line voltage. the dynamic response to changing load conditions is very fast. the time bet ween measurement and action is only a fraction of a power cycle. the voltage measurement comes during the switch off time of every cycle, and controls the on time switching decision for the very next cycle. pulsetrain therefore reacts almost instantaneousl y to changes in load and line conditions. the mechanism of real - time waveform analysis provides inherent stability without the need for loop compensation. the expense of loop compensation components and the design time they represent are eliminated. 11.4 power factor correction one very welcome result of the pulsetrain methodology is that topologies that have proven problematical with pwm/pfm controllers work smoothly with pulsetrain. for example, the IW2202 is ideal for use in the in herently pfc - corrected bifred (boost integrated with flyback rectifier/energy storage/dc - dc) topology. the basic bifred topology uses a discontinuous mode boost converter to achieve pfc. the capacitor of the boost converter is used as a bulk capacitor to drive a flyback converter. bifred uses a single switch. see figure 8 . l 1 q 1 t 1 vout c 2 d 5 bulk capacitor switch c 1 boost inductor flyback windings figure 8 . bifred circuit the circuit operates as follows: switch on: energy derived from the ac line is stored in the boost inductor. at the same time, energy derived from the bulk capacitor is stored in the primary of the flyback transformer. switch off: the energy in the flyback primary is transferred to the output. at the same time, the energy in the boos t inductor is delivered to the bulk capacitor, charging it. if the two inductors store the same amount of energy, on average, over the course of a half - cycle of the ac input, the voltage of the bulk capacitor will remain constant. the IW2202 achieves this goal, avoiding the problem of high voltage stresses on the bulk capacitor. with traditional controllers (such as modified pfm), the bulk capacitor voltages tend to www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 10 become very high under some line and load conditions. with the IW2202 , the voltages remain under 400v at all times, allowing standard capacitors to be used. this is a direct benefit of using pulsetrain technology. both the boost stage and the flyback stage operate in discontinuous mode. this m eans that both inductors are fully reset once per switching cycle. the energy stored in the boost inductor is completely transferred to the bulk capacitor, and the energy stored in the flyback transformer is completely transferred to the load. input current input voltage figure 9 . power factor correction example 11.5 smartsk ip mode s smartskip sense pulses power pulses sense pulses smart skip vgate vpri figure 10 . smartskip mode as has already been mentioned, a sense pulse delivers one - sixteenth as much energy as a power pulse. a continuous stream of sense pulses thus delivers 6.25% of full load. if the load is lighter than this, the device enters smartskip mode, when the circuit alternates between sense pulses and no pulses at all. regulation is s till maintained, since each sense pulse returns a precise measurement of output voltage. smartskip mode is entered automatically when the sense pulses reveal that the output voltage is remaining above the desired level, though no power pulses have been sen t recently. the depth of the smartskip mode (the ratio of skipped cycles to sense pulses) is increased or decreased, according to voltage and the current skip - mode depth. the depth of the smartskip mode is reduced automatically as the load increases. vgate vpri normal mode (power pulses and sense pulses) smartskip mode (sense pulses and skipped pulses) figure 11 . depth of smartskip increasing with light load 11.6 soft - start and protection in pulsetrain, all output switching occurs as the result of the pulsetrain logic. if the logic is not up and running, th e output switch is always off. valid waveform analysis is available by the second power pulse. this reduces the problem of soft - start merely to the requirement that there be a reliable power - on reset mechanism. figure 12 shows wha t happens on the output at start - up. the first power pulse shows a clean current ramp, but the drain voltage reflects the fact that the transformer does not reset by the time the second pulse arrives, and thus is operating in continuous mode. this is also shown in the current on the second pulse, which starts at a non - zero value. however, pulsetrain?s automatic peak current limiting causes the second power pulse to be much shorter than the first one. by the third cycle, the initial current has already falle n significantly, due to www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 11 the second cycle?s shorter on time. this trend will continue until, in a few cycles, the initial current is zero and the transformer is operating in critically discontinuous mode. vgate ipri vdrain figure 12 . example of current limiting during start - up the nominal vcc voltage of the device is 12 volts. it requires a start - up voltage that reaches 14 momentarily, initiating a start - up sequence internally. the device protects itself from over - voltage by shutting itself down if vcc exceeds 15 volts. its under - voltage lockout circuit will cause it to shut itself down if the voltage drops below 7.8 volts, and will remain shut down until the start - up voltage is seen a gain. both over - and under - voltage shutdowns inhibit switching on the output pin. these mechanisms protect the device, while protecting the rest of the circuit indirectly. additional protection can be achieved with external sensors that shut down the IW2202 on a circuit fault. the best way of shutting down the IW2202 is to pull the isense pin above 1.5v. this will inhibit output pulses. 12 designing IW2202 - based power supplies the schematic in figure 2 shows a typical IW2202 system. choosing component values is a straightforward process, as shown in the example below. 12.1 description for this example, we are designing an 70w, 19v laptop computer power supply. it is a universal input supply supporting input line voltages of 85 - 265 vrms, and operating in discontinuous flyback mode. to keep component costs low, we wish to use a switch with a maximum vdrain of no more than 600v. 12.2 primar y turns ratio the voltage across a flyback switch includes the input voltage plus the reflected secondary voltage: vd = vin + n*vout. the turns ratio between the primary and secondary, n, is constrained by our desire to avoid stressing the switch. we use the maximum safe value of vd and the highest input voltage for our worst - case calculation: vd_max = vline_max + n*vsec n = (vd_max ? vline_max)/vsec 12.2.1 example if we use a 600v switch and derate it by 100v as a safety margin, we are left with 500v as our maxi mum drain voltage, vd_max. n = (500v - 380v)/19.7v = 6.09 ? 6. 12.3 ipeak selection we next need to calculate the peak current value we need to support worst - case operation. the constant peak current circuitry will keep the output switch on until this value is r eached on every power cycle. iin is the average input current to the converter: iin = po/(vin* h ) where h is the efficiency of the converter. vsec is the secondary voltage. it differs from the output voltage, www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 12 vout, by a fixed d v, where d v is the secondary d iode drop. we will use 0.7v for d v, and thus a vsec of 19.7v in our example. the maximum input current we must support occurs at minimum supported line voltage: iin = po/(vin_min* h ) vin_min = vline_min*1.4142 vline_min is the lowest supported rms line vol tage. full - load efficiency can be taken as a (slightly conservative) 0.80 for design purposes. we need to convert the average input current iin into a peak input current ipeak. this depends on the duty cycle, d, of the switch and the shape of the primary current waveform (a triangle wave with a peak value of twice the average value): ipeak = 2*iin/d at low line voltage, d is: d_ll = ton_ll/(ton_ll+toff_ll) ton_ll is the maximum on time, which we will set to 5.5 m s. (the device will limit the on time to 6 m s if ipeak is not reached.) since, in a critically discontinuous - mode flyback converter, the net transformer volt - seconds are zero: vpri*ton = n*vsec*toff, we can solve for toff: toff_ll = vin_min*ton_ll/(n*vsec) example vin_min = 85*1.4142 = 120.21 v tof f_ll = 120.21*5.5x10 - 6 /(6*19.7) = 5.6x10 - 6 s iin = 70/(120.21*0.80) = 0.728 a d_ll = 5.5x10 - 6 s/(5.5x10 - 6 s+5.6x10 - 6 s) = 0.495 f_sw = 1/(5.5x10 - 6 s+5.6x10 - 6 s) = 90 khz ipeak = 2*0.728/0.495 = 2.94 a 12.3.1 ipeak resistors the ipeak resistors consist of a sense resist or (r6) and a voltage divider (r4 and r5). the isense pin is a voltage amplifier with a gain of 5.0 that compares the amplified voltage to a reference of 1.2 v. resistors r4, r5, and r6 are chosen to scale the voltage accordingly. example we choose 0.1 w for r6. the voltage across r6 at ipeak is: 0.1*2.94 = 0.294 v. we need the voltage at the isense pin, vc_pk, to be 1.2 /5 or 0.24 when ipeak is reached. if we choose r4 to be 2.2 k w , then r5 = r4*(ipeak*r6*gain ? vref)/vref = 495 12.4 primary inductance the inductance of the primary winding is based on the lowest supported line voltage, the longest on time, and the peak current: lp = vin_min * ton_max/ipeak example our design calls for an lp of lp = 120.21 * 5.5x10 - 6 / 2.94 = 225 m h 12.5 auxiliary turns ratio the turns ratio between secondary and auxiliary winding is set to give 12v output plus a 0.6v diode drop to provide power to the chip: naux/nsec = 12.6/vout 12.6 vaux resistors the output voltage is set by the resistor divider, r1 and r 2, across the auxiliary winding voltage (vauxw). the divided voltage is fed into the vaux pin. a schottky diode, d2, is used as a clamping diode in parallel with r2, to minimize negative voltages on the vaux pin. vsec = vauxw * (nsec/naux) voltage regulati on is controlled by the resistor divider and the IW2202 ?s internal voltage reference, which is fixed at 1.2 v. the voltage on the vaux pin is compared with the reference by the real - time waveform analysis circuitry. if it is above this level, www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 13 the next cycle will be a sense cycle. if it is below this level, the next cycle will be a power cycle: vauxw = vref * (r1+r2)/r2 vsec = 1.2 * (( r1+r2)/r2 * (nsec/naux)) example continuing our example, we see that nsec/ naux = 19.7/12.6. to find r1 and r2, we first note that: vauxw = vref(1 + r1/r2) , r1 = (vauxw ? vref)*r2/vref if we arbitrarily set r2 to 1.1 k w , we have: r1 = (12.6 - 1.2 )*1100/ 1.2 = 10.45 k w 12.7 pfc choke and capacitor in the bifred topolo gy used in this design, there is a definite relationship between the flyback primary inductance (lp), the boost inductance (l1), and the boost capacitor (c1) voltage: l1 = ( h *vin_rms 2 *l2)/vc1 2 we would like the bulk capacitor voltage to be no more than th e peak input voltage: vc1 = vin_rms* 2 by substituting vin_rms* 2 for vc1, we get: l1 = h *lp/2 other implementations of the bifred technology operate at elevated capacitor voltages, but this does not occur with a p ulsetrain controller. the size of the bulk capacitor is based on ripple voltage requirements. we have used 2 m f per watt of output power as a starting point. example in our design: l1 = 0.80*225 m h/2 = 90 m h c1 = 2.0*70 = 140 m f 12.8 vin resistors the pin sensing line voltage uses a fixed resistor divider consisting of r7 and r8. r7 = 500 k w ; r8 = 1 k w . 12.9 conclusion this example shows the simplicity of designing a power supply with an iwatt pulsetrain controller. in particular, note the complete absence of loop com pensation, eliminating the time and costs associated with loop compensation design. we have also eliminated optoisolators and their associated feedback circuitry, reducing costs and pc board area. finally, pfc features have been added with a minimum of cos t and design effort. www.datasheet.co.kr datasheet pdf - http://www..net/
IW2202 data sheet preliminary data revision 1.1 page 14 13 physical dimensions figure 13 . physical dimensions, so - 8 package 14 about iwatt iwatt inc. is a fabless semiconductor company that develops power management ics for computer, commu nication, and consumer markets. the compa ny?s patented pulsetrain ? technology, the industry?s first truly digital approach to power system regulation, is revolutionizing power supply design. trademark information iwatt and pulsetrain are trademarks of iwatt, inc. contact information web: http://www.iwatt.com e - mail: sales@iwatt.com phone : 408 - 374 - 4200 fax: 408 - 341 - 0455 iwatt corporation 90 albright way los gatos ca 95032 disclaimer iwatt reserves the right to make cha nges to its products and to discontinue products without notice. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). iwatt semiconduc tor products are not designed, intended, authorized, or warranted to be suitable for use in life - support applications, devices or systems, or other critical applications. inclusion of iwatt products in critical applications is understood to be fully at the risk of the customer. questions concerning potential risk applications should be directed to iwatt through an iwatt sales office. iwatt semiconductors are typically used in power supplies in which high voltages are present during operation. high - voltage s afety precautions should be observed in design and operation to minimize the chance of injury. www.datasheet.co.kr datasheet pdf - http://www..net/

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